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HT47C20 8-Bit R-F Type Mask MCU
Features
* Operating voltage: 2.4V~3.6V * Eight bidirectional I/O lines * Four input lines * One interrupt input * One 16-bit programmable timer/event counter with * HALT function and wake-up feature reduce power
consumption
* LCD bias C type * One LCD driver with 20 3 or 19 4 segments * One 38kHz or 40kHz IR carrier output
PFD (programmable frequency divider) function
* On-chip crystal and RC oscillator for system clock * One 32.768kHz crystal oscillator for real time clock * Watchdog Timer * 2K16 program memory ROM * 648 data memory RAM * One Real Time Clock (RTC) * One 8-bit prescaler for RTC * One buzzer output
(455kHz or 480kHz system clock only)
* Two channels RC type A/D converter * Four-level subroutine nesting * Bit manipulation instruction * 16-bit table read instruction * Up to 8.3ms instruction cycle with 480kHz system
clock
* All instructions in one or two machine cycles * 63 powerful instructions * 64-pin QFP package
General Description
The HT47C20 is an 8-bit high performance RISC-like microcontroller. Its single cycle instruction and two-stage pipeline architecture make high speed applications. The device is suited for use in multiple LCD low power applications among which are calculators, clock timers, games, scales, toys, thermometers, hygrometers, body thermometers, capacitor scaler, other hand held LCD products, and battery systems in particular.
Rev. 1.60
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July 26, 2002
HT47C20
Block Diagram
P B 0 /IN T S y s te m M In te rru p t C ir c u it P ro g ra m ROM P ro g ra m C o u n te r STACK IN T C T im e r B U X T im e r A O v e r flo w A /D T1 C lo c k
R T C O u tp u t P B 2 /T M R P.D C lo c k IN 0 CS RS CR RT IN 1 CS RS RT 0 1 1 1 0 0 T0 P A 3 /P . D
In s tr u c tio n R e g is te r
MP
M U
X
DATA M e m o ry
A /D
R C Type C o n v e rte r
In s tr u c tio n D ecoder ALU T im in g G e n e ra to r
MUX
RTC STATUS W DT T im e B a s e M U X
S Y S C L K /4 RTC OSC OSC3 OSC4
S h ifte r
W DT OSC P o rt B
BP OSC2 OS RE VD VS S S D C1 ACC LCD M e m o ry H a lv e V o lta g e L C D D r iv e r PA V1 V2 V3 C O M 0~ COM2 C O M 3/ SEG 19 SEG 0~ SEG 18 PB
P B 0 /IN T PB1 P B 2 /T M R PB3
C1 C2
P o rt A
PA0 PA1 PA2 PA3 PA4
/B /B /IR /P ~P
Z Z
.D A7
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HT47C20
Pin Assignment
OSC4 OSC3 OSC2 OSC1 VDD
RES
NC
NC
P A 0 /B Z
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
64 63 62 61 60 59 58 57 56 55 54 53 52
C1
C2
V2
V3 51 50 49 48 47 46 45 44 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18
V1
P A 1 /B Z P A 2 /IR P A 3 /P . D PA4 PA5 PA6 PA7 P B 0 /IN T PB1 P B 2 /T M R PB3 NC NC NC NC NC NC VSS
H T47C 20 6 4 Q . P -A
43 42 41 40 39 38 37 36 35 34 33
20 21 22 23 24 25 26 27 28 29 30 31 32
IN 0
COM0
COM1
COM2
C O M 3 /S E G 1 9
CS0
RS0
IN 1
CRT0 RT0
CS1 RS1
RT1
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HT47C20
Pad Assignment
OSC1 56 M C LR PA0 PA1 PA2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 COM0 25 COM1 (0 , 0 ) PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 VSS 3 1 2 RT1 OSC2 55 RS1 CS1 OSC3 53 RT0 OSC4
* The IC substrate should be connected to VSS in the PCB layout artwork.
VDD 54 IN 1
C1
C2
V1 48 49 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 COM2 V2 V3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 COM3
52
51
50
CRT0
RS0
CS0
IN 0
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HT47C20
Pad Description
Pad No. 1 Pad Name RES I/O I Mask Option 3/4 Function Schmitt trigger reset input. Active low.
2 3 4 5 6~9
PA0/BZ PA1/BZ PA2/IR PA3/PFD PA4~PA7
I/O
Bidirectional 8-bit input/output port. The low nibble of the PA can be configured as CMOS output or NMOS output with or without Wake-up pull-high resistors (mask option). NMOS output can be configured Pull-high as Schmitt trigger input with or without pull-high resistors. Each bit of or None NMOS output can be configured as wake up input by mask option. CMOS or Of the eight bits, PA0~PA1 can be set as I/O pins or buzzer outputs by mask option. PA2 can be set as an I/O pin or an IR carrier output NMOS also by mask option. PA3 can be set as an I/O pin or a PFD output also by mask option. Four-bit Schmitt trigger input port. The PB is configured as with pull-high resistors. Of the four bits, PB0 can be set as an input pin or an external interrupt input pin (INT) by software application. While PB2 can be set as an input pin or a timer/event counter input pin also by software application. Negative power supply, ground Oscillation input pin of channel 1 Reference capacitor connection pin of channel 1 Reference resistor connection pin of channel 1 Resistor sensor connection pin for measurement of channel 1 Oscillation input pin of channel 0 Reference capacitor connection pin of channel 0 Reference resistor connection pin of channel 0 Resistor/capacitor sensor connection pin for measurement of channel 0 Resistor sensor connection pin for measurement of channel 0
10 11 12 13 14 18 17 16 15 23 22 21 20 19 27 26~24 28~46
PB0/INT PB1 PB2/TMR PB3 VSS IN1 CS1 RS1 RT1 IN0 CS0 RS0 CRT0 RT0 SEG19/COM3 COM2~COM0 SEG18~SEG0
I
3/4
3/4 I O O O I O O O O O O 3/4 O I 3/4 O I
3/4
3/4
3/4
SEG19/COM3 can be set as a segment or a common output driver 1/3 or 1/4 for LCD panel by mask option. COM2~COM0 are outputs for LCD Duty panel plate. 3/4 3/4 3/4 3/4 LCD driver outputs for LCD panel segments Voltage pump Real time clock oscillators Positive power supply
49, 48, 47 V1, V2, V3 51, 50 C1, C2 52 53 54 55 56 OSC4 OSC3 VDD OSC2 OSC1
Crystal or OSC1 and OSC2 are connected to an RC network or a crystal RC (by mask option) for the internal system clock.
Absolute Maximum Ratings
Supply Voltage .........................................-0.3V to 5.5V Storage Temperature ............................-50C to 125C Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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HT47C20
D.C. Characteristics
Symbol VDD IDD1 IDD2 Parameter Operating Voltage Operating Current (Crystal OSC) Operating Current (RC OSC) Standby Current (32.768kHz Crystal Oscillator Enable, LCD Off) Standby Current (32.768kHz Crystal Oscillator Enable, LCD On) Standby Current (Watchdog RC Oscillator Enable, LCD Off) Standby Current (Watchdog RC Oscillator Enable, LCD On) Standby Current (32.768kHz Crystal and Watchdog RC Oscillator Both Disabled, LCD Off) Standby Current (A/D On, *R=5kW, *f=500kHz) Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input Low Voltage (INT, TMR) Input High Voltage (RES, INT, TMR) I/O Port Sink Current I/O Port Source Current Common 0~3 Output Sink Current Common 0~3 Output Source Current Segment 0~19 Output Sink Current Segment 0~19 Output Source Current Common 0~3 Output Sink Current Common 0~3 Output Source Current Segment 0~19 Output Sink Current Segment 0~19 Output Source Current RC Oscillation Output Sink Current RC Oscillation Output Source Current Pull-high Resistance of I/O Ports and INT Test Conditions VDD 3/4 3V 3V Conditions 3/4 No load, fSYS=455kHz A/D Off No load, fSYS=455kHz A/D Off Min. 2.4 3/4 3/4 3/4 Typ. 3 0.2 0.2 Max. 3.6 0.4 0.4 Ta=25C Unit V mA mA
ISTB1
3V No load, system HALT
3/4
3
mA
ISTB2
3V No load, system HALT
3/4 3/4 3/4 3/4 3/4 0 2.1 0 0 2.4 2 -1 50 -50 15 -15 100 -100 20 -20 5 -5
3/4 3/4 3/4 3/4
5
mA mA mA mA mA V V V V V mA mA mA mA mA mA mA mA mA mA mA mA kW
ISTB3 ISTB4
3V No load, system HALT 3V No load, system HALT
7 10
ISTB5
3V No load, system HALT
1
ISTB6 VIL1 VIH1 VIL2 VIL3 VIH2 IOL IOH IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 IOL4 IOH4 IOL5 IOH5 RPH Note:
3V No load, system HALT 3V 3V 3V 0.5VDD 3V 0.3VDD 3V 0.8VDD 3V VOL=0.3V 3V VOH=2.7V 3V VOL=0.3V (1/2 bias) 3V VOH=2.7V (1/2 bias) 3V VOL=0.3V (1/2 bias) 3V VOH=2.7V (1/2 bias) 3V VOL=0.45V (1/3 bias) 3V VOH=4.05V (1/3 bias) 3V VOL=0.45V (1/3 bias) 3V VOH=4.05V (1/3 bias) 3V VOL=0.3V 3V VOH=2.7V 3V 3/4 3/4 3/4
600 3/4 3/4 3/4 3/4 3/4 3.5 -1.5 100 -100 30 -30 180 -180 40 -40 10 -10 60
1200 0.9 3 1.5 0.9 3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 80
40
*R stands for the resistance of RC type A/D converter *f stands for the frequency of RC type A/D converter
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HT47C20
A.C. Characteristics
Symbol fSYS1 fSYS2 fTIMER tWDTOSC tRES tSST tINT fAD Parameter System Clock (Crystal OSC) System Clock (RC OSC) Timer I/P Frequency (TMR) Watchdog Oscillator External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width A/D Converter Frequency Test Conditions VDD 3V 3V 3V 3V 3/4 3/4 3/4 3V Conditions 3/4 3/4 3/4 3/4 3/4 Power-up or wake-up from HALT 3/4 3/4 Min. 455 64 0 45 10 3/4 10 3/4 Typ. 3/4 3/4 3/4 90 3/4 1024 3/4 3/4 Max. 480 500 500 180 3/4 3/4 3/4 500 Ta=25C Unit kHz kHz kHz ms ms tSYS ms kHz
Note: tSYS=1/fSYS
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HT47C20
Functional Description
Execution flow The system clock for the HT47C20 is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program counter - PC The 11-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a maximum of 2048 addresses. After accessing a program memory word to fetch an instruction code, the contents of the program counter are
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required.
S y s te m
C lo c k
In s tr u c tio n C lo c k PC PC PC+1 PC+2
. e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
. e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
. e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution flow
Mode Initial Reset External Interrupt Time Base Interrupt RTC Interrupt Timer/event Counter Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter *10 0 0 0 0 0 *10 #10 S10 *9 0 0 0 0 0 *9 #9 S9 *8 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 @6 #6 S6 *5 0 0 0 0 0 PC+2 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 *4 0 0 0 0 1 *3 0 0 1 1 0 *2 0 1 0 1 0 *1 0 0 0 0 0 *0 0 0 0 0 0
Program counter Note: *10~*0: Program counter bits S10~S0: Stack register bits #10~#0: Instruction code bits @7~@0: PCL bits
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HT47C20
Program memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 204816 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage
* Location 000H * Location 00CH
This area is reserved for the real time clock interrupt service program. If a real time clock interrupt results from a real time clock overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
This area is reserved for the initialization program. After chip reset, the program always begins execution at location 000H.
* Location 004H
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a Timer/Event Counter A or B overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010H.
* Table location
This area is reserved for the external interrupt service program. If the INT input pin is activated, and the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
This area is reserved for the time base interrupt service program. If time base interrupt results from a time base overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
000H 004H 008H 00C H 010H D e v ic e in itia liz a tio n p r o g r a m E x te r n a l in te r r u p t s u b r o u tin e T im e b a s e in te r r u p t s u b r o u tin e R T C in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r in te r r u p t s u b r o u tin e P ro g ra m ROM
n00H n..H
L o o k - u p ta b le ( 2 5 6 w o r d s )
7..H
L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 6 b its N o te : n ra n g e s fro m 0 to 7
Any location in the ROM space can be used as look up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions need two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements.
Program memory
Instruction(s) TABRDC [m] TABRDL [m]
Table Location *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table location Note: *10~*0: Table location bits P10~P8: Current program counter bits @7~@0: Table pointer bits
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HT47C20
Stack register - STACK This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into four levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent four return addresses are stored). Data memory - RAM The data memory is designed with 83 8 bits. The data memory and is divided into two functional groups: special function registers and general purpose data memory (64 8). Most are read/write, but some are read only. The special function registers include the indirect addressing register 0 (00H), the memory pointer register 0 (mp0; 01H), the indirect addressing register 1 (02H), the memory pointer register 1 (MP1;03H), the bank pointer (BP;04H), the accumulator (ACC;05H), the program counter lower-order byte register (PCL;06H), the table pointer (TBLP;07H), the table higher-order byte register (TBLH;08H), the real time clock control register (RTCC;09H), the status register (STATUS;0AH), the interrupt control register 0 (INTC0;0BH), the I/O registers (PA;12H, PB;14H), the interrupt control register 1 (INTC1;1EH), the Timer/Event Counter A higher order byte register (TMRAH; 20H), the Timer/Event Counter A lower order byte register (TMRAL; 21H), the timer/event counter control register (TMRC; 22H), the Timer/Event Counter B higher order byte register (TMRBH; 23H), the Timer/Event Counter B lower order byte register (TMRBL; 24H), and the RC oscillator type A/D converter control register (ADCR; 25H). The remaining space before the 40H are reserved for future expanded usage and reading these location will return the result 00H. The general purpose data memory, addressed from 40H to 7FH, is used for data and control information under instruction command.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0.H 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1.H 20H 21H 22H 23H 24H 25H 26H 40H G e n e ra l P u rp o s e D a ta M e m o ry (6 4 B y te s ) 7.H IN T C 1 TM RAH TM RAL TM RC TM RBH TM RBL ADCR PB PA S p e c ia l P u r p o s e D a ta M e m o ry In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0
:U nused
R e a d a s "0 0 "
RAM mapping (bank 0)
All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instruction, respectively. They are also indirectly accessible through memory pointer registers (MP0;01H, MP1;03H).
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Indirect addressing register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly will return the result 00H. Writing indirectly results in no operation. The function of data movement between two indirect addressing registers are not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers which can be used to access the data memory by combining corresponding indirect addressing registers. Only MP0 can be applied to data memory, while MP1 can be applied to data memory and LCD display memory. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
Status register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD) and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PD flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PD flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PD flags can only be changed by the Watchdog Timer overflow, system power-up, clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupts The HT47C20 provides an external interrupt, an internal timer/event counter interrupt, an internal time base interrupt, and an internal real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits to set the enable/disable and interrupt request flags.
The ALU not only saves the results of a data operation but can change the status register.
Labels C
Bits 0
Function C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD is cleared when either a system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Unused bit, read as 0 STATUS register
AC Z OV PD TO 3/4 3/4
1 2 3 4 5 6 7
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Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval, but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the EMI bit and the corresponding bit of INTC0 or INTC1 may be set allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupt have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then by branching to subroutines at specified location(s) in the program memory. Only the program counter is pushed onto the stack. If the contents of the register and status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents must be saved first. External interrupt is triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit 4 of INTC0) will be set. When the interrupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 4 of INTC1), caused by a timer A or timer B overflow. When the interrupt is enabled, and the stack is not Register Bit No. 0 1 2 INTC0 (0BH) 3 4 5 6 7 0 1 2 INTC1 (1EH) 3 4 5 6 7 Label EMI EEI ETBI ERTI EIF TBF RTF 3/4 ETI 3/4 3/4 3/4 TF 3/4 3/4 3/4 full and the TF bit is set, a subroutine call to location 10H will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts. The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 5 of INTC0), caused by a regular time base signal. When the interrupt is enabled, and the stack is not full and the TBF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TBF) will be reset and the EMI bit cleared to disable further interrupts. The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 6 of INTC0), caused by a regular real time clock signal. When the interrupt is enabled, and the stack is not full and the RTF bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag (RTF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Function Control the master (global) interrupt (1= enabled; 0= disabled) Control the external interrupt (1= enabled; 0= disabled) Control the time base interrupt (1= enabled; 0= disabled) Control the real time clock interrupt (1= enabled; 0= disabled) External interrupt request flag (1= active; 0= inactive) Time base request flag (1= active; 0= inactive) Real time clock request flag (1= active; 0= inactive) Unused bit, read as 0 Control the timer/event counter interrupt (1= enabled; 0=disabled) Unused bit, read as 0 Unused bit, read as 0 Unused bit, read as 0 Internal timer/event counter request flag (1= active; 0= inactive) Unused bit, read as 0 Unused bit, read as 0 Unused bit, read as 0 INTC register
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HT47C20
No. a b c d Interrupt Source External interrupt Time base interrupt Real time clock interrupt Timer/event counter interrupt Priority Vector 1 2 3 4 04H 08H 0CH 10H
OSC2 C r y s ta l O s c illa to r RC OSC2 O s c illa to r OSC1 OSC1
The external interrupt request flag (EIF), real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), enable external interrupt bit (EEI), enable real time clock interrupt bit (ERTI), enable time base interrupt bit (ETBI), and enable master interrupt bit (EMI) constitute an interrupt control register 0 (INTC0) which is located at 0BH in the data memory. The timer/event counter interrupt request flag (TF), enable timer/event counter interrupt bit (ETI) on the other hand, constitute an interrupt control register 1 (INTC1) which is located at 1EH in the data memory. EMI, EEI, ETI, ETBI, and ERTI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt being serviced. Once the interrupt request flags (RTF, TBF, TF, EIF) are set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Because interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications, if only one stack is left, and enabling the interrupt is not well controlled, once the CALL subroutine operates in the interrupt subroutine will damage the original control sequence. Oscillator configuration There are two oscillator circuits in the HT47C20. Both are designed for system clocks; the RC oscillator and the crystal oscillator, which are determined by mask option. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. The OSC1 and OSC2 are at the same level when the system enters the power down mode. If an RC oscillator is used, an external resistor between OSC1 and OSC2 is need and the resistance must range from 51kW to 1MW. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. If a crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift needed for oscillator, no other external components are needed. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required.
System oscillator There is another oscillator circuit designed for the real time clock. In this case, only the 32768kHz crystal oscillator can be applied. The crystal should be connected between OSC3 and OSC4, and two external capacitors along with one external resistor are required for the oscillator circuit in order to get a stable frequency. The RTC oscillator circuit can be controlled to oscillate quickly by setting SAVE bit (bit 4 of RTCC) to 0. After power on reset, the SAVE bit initial value is 0 that is on the quick-oscillate mode. Its recommended to turn it off by setting the SAVE bit 1 after a period of about 2 secondstoavoiddrainingextrapower.
OSC3 32768H z OSC4
RTC oscillator The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 90ms. The WDT oscillator can be disabled by mask option to conserve power. Watchdog Timer - WDT The clock source of the WDT(fS) is implemented by a dedicated RC oscillator (WDT oscillator) or a instruction clock (system clock divided by 4) or a real time clock oscillator (RTC oscillator), decided by mask options. The timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by a mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. If the clock source of WDT chooses the internal WDT oscillator, the time-out period may vary with temperature, VDD, and process variations. On the other hand, if the clock source selects the instruction clock and the HALT instruction is executed, WDT may stop counting and lose its protecting purpose, and the logic can only be restarted by external logic. When the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT can cease the system clock.
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HT47C20
S y s te m C lo c k /4 M ask O p tio n S e le c tio n fS D iv id e r fS /2
8
RTC O SC 32768H z W DT 12kH z OSC
P r e s c a le r W D T C le a r
CK R
T
CK R
T
T im e - o u t R e s e t fS /2 1 5 ~ fS /2 1 6
Watchdog Timer The WDT overflow under normal operation will initialize chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a warm reset only the PC and SP are reset to zero. To clear the contents of WDT, three methods are adopted, external reset (a low level to RES), software instruction, or a HALT instruction. The software instructions are of two types which include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the mask option - CLR WDT times selection option. If the CLR WDT is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case CLR WDT1 and CLR WDT2 are chosen (i.e. CLR WDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip because of time-out. The WDT time-out period ranges from fS/215~fS/216. Bec a u s e t h e C L R W D T o r C LR W D T 1 a n d CLRWDT2 instruction only clear the last two-stage of the WDT. Multi-function timer The HT47C20 provides a multi-function timer for WDT, time base and real time clock but with different time-out periods. The multi-function timer consists of a 7-stage divider and an 8-bit prescaler, with the clock source coming from WDT OSC or RTC OSC or the instruction clock (i.e., system clock divided by 4). The multi-function timer also provides a selectable frequency signal (ranges from fS/22 to fS/28) for LCD driver circuits, and a selectable frequency signal (ranges from fS/22 to fS/29) for buzzer output by mask option. It is recommended to select a near 4kHz signal for LCD driver circuits for proper display. Time base The time base offers a periodic time-out period to generfS D iv id e r fS /2
8
ate a regular internal interrupt. Its time-out period ranges from fS/212 to fS/215 selected by mask option. If time base time-out occurs, the related interrupt request flag (TBF; bit 5 of INTC0) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 08H occurs. When the HALT instruction is executed, the time base still works (if WDT clock source comes from WDT RC OSC or RTC OSC) and can wake up from HALT mode. If the TBF is set 1 before entering the HALT mode, the wake up function will be disable. Real time clock - RTC The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by software programming . Writing data to RT2, RT1 and RT0 (bits 2, 1, 0 of RTCC;09H) yields various time-out periods. If the RTC time-out occurs, the related interrupt request flag (RTF; bit 6 of INTC0) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 0CH occurs. The real time clock time-out signal can also be applied to be a clock source of timer/event counter, so as to get a longer time-out period. RT2 0 0 0 0 1 1 1 1 RT1 0 0 1 1 0 0 1 1 RT0 0 1 0 1 0 1 0 1 RTC Clock Divided Factor 28 29 210 211 212 213 214 215
P r e s c a le r L C D D r iv e r f S /2
2 8
M a s k O p tio n T im e B a s e In te r r u p t fS /2 1 2 ~ fS /2 1 5
~ fS /2
B uzzer fS /2 2 ~ fS /2
9
Time base
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HT47C20
fS D iv id e r RT2 RT1 RT0 fS /2
8
P r e s c a le r fS /2 ~ fS /2 R T C In te rru p t
8 15
8 to 1 M ux.
Real time clock Power down operation - HALT The HALT mode is initialized by the HALT instruction and results in the following.
* The system oscillator will turn off but the WDT oscilla-
To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset
* There are three ways in which a reset may occur. * RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
tor or RTC oscillator keeps running (if the WDT oscillator or the real time clock is selected).
* The contents of the on-chip RAM and registers remain
unchanged.
* The WDT will be cleared and recounted again (if the
WDT clock comes from the WDT oscillator or the real time clock oscillator). * All I/O ports maintain their original status.
* The PD flag is set and the TO flag is cleared. * LCD driver is still running by mask option (if the WDT
OSC or RTC OSC is selected). The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. Examining the TO and PD flags, the reason for chip reset can be determined. The PD flag is cleared when the system power-up or executing the CLR WDT instruction and is set when the HALT instruction is executed. The TO flag is set if a WDT time-out occurs, it causes a wake-up that only resets the PC and SP, the others maintain their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after the wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by one more cycle. If the wake-up results in the next instruction execution, this will execute immediately after a dummy period has finished. Rev. 1.60 15
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm reset that just resets the PC and SP leaving the other circuits in their original state. Some registers remain unchanged during any other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PD and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PD 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
Note: u means unchanged. To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra delay. There is an extra delay of 1024 system clock pulses when the system awakes from the HALT state or when the system powers up. The functional unit chip reset status are shown below. PC Interrupt Prescaler, Divider 000H Disabled Cleared
Clear. After master reset, WDT, RTC, Time Base begin counting Timer/event Counter Input/output Ports SP
VDD RES S S T T im e - o u t C h ip R e s e t tS
ST
Off Input mode Points to the top of the stack
Reset timing chart
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HT47C20
HALT W DT W DT T im e - o u t R eset E x te rn a l SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n C o ld R eset W a rm R eset
V
DD
RES
RES
OSC1
Reset circuit
Reset configuration
The states of the registers are summarized in the following table: Register TMRAH TMRAL TMRC TMRBH TMRBL ADCR Program Counter MP0 MP1 ACC TBLP TBLH STATUS INTC0 INTC1 RTCC PA Note: Reset (power on) xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx -000 0000 ---0 ---0 --x0 0111 1111 1111 WDT time-out (normal operation) uuuu uuuu uuuu uuuu 0000 1--uuuu uuuu uuuu uuuu 1xxx --00 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu -000 0000 ---0 ---0 --x0 0111 1111 1111 RES reset (normal operation) uuuu uuuu uuuu uuuu 0000 1--uuuu uuuu uuuu uuuu 1xxx --00 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu -000 0000 ---0 ---0 --x0 0111 1111 1111 RES reset (HALT) uuuu uuuu uuuu uuuu 0000 1--uuuu uuuu uuuu uuuu 1xxx --00 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --01 uuuu -000 0000 ---0 ---0 --x0 0111 1111 1111 WDT time-out (HALT) uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu uuuu --uu 000H* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu ---u ---u --uu uuuu uuuu uuuu
* refers to warm reset u means unchanged x means unknown
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HT47C20
Timer/event counter One 16-bit timer/event counter with PFD output or two channels of RC type A/D converter is implemented in the HT47C20. The ADC/TM bit (bit 1 of ADCR register) decides whether timer A and timer B is composed of one 16-bit timer/event counter or timer A and timer B composedoftwochannelsRCtypeA/Dconverter. The TMRAL, TMRAH, TMRBL, TMRBH compose one 16-bit timer/event counter, when ADC/TM bit is 0. The TMRBL and TMRBH are timer/event counter preload registers for lower-order byte and higher-order byte respectively. Using the internal clock, there are three reference time-base. The timer/event counter internal clock source may come from the system clock or system clock/4 or RTC time-out to generate an accurate time base. Using external clock input allows the user to count external events, count external RC type A/D clock, measure time intervals or pulse widths, or generate an accurate time base. There are six registers related to the timer/event counter operating mode. TMRAH ([20H]), TMRAL ([21H]), TMRC ([22H]), TMRBH ([23H]), TMRBL ([24H]) and ADCR ([25H]). Writing TMRBL only writes the data into a low byte buffer, and writing TMRBH will write the data and the contents of the low byte buffer into the time/event counter preload register (16-bit) simultaneously. The timer/event counter preload register is changed by writing TMRBH operations and writing TMRBL will keep the timer/event counter preload register unchanged. Reading TMRAH will also latch the TMRAL into the low byte buffer to avoid the false timing problem. Reading TMRAL returns the contents of the low byte buffer. In other words, the low byte of the timer/event counter can not be read directly. It must read the TMRAH first to make the low byte contents of the timer/event counter be latched into the buffer. If the timer/event counter is on, the TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written to. To avoid conflicting between timer A and timer B, the TMRAH, TMRAL, TMRBH and TMRBL registers
S y s te m C S y s te m C lo A /D C RTC TM R0 TE 1 6 - b it T im e r B TN2 TN1 TN0 lo ck lo O ck /4 ck ut M U X 1 6 - b it T im e r A
should be accessed with MOV instruction under timer off condition. The TMRC is the timer/event counter control register, which defines the timer/event counter options. The timer/event counter control register defines the operating mode, counting enable or disable and active edge. Writing to timer B makes the starting value be placed in the timer/event counter preload register, while reading timer A yields the contents of the timer/event counter. Timer B is timer/event counter preload register. The TN0, TN1 and TN2 bits define the operation mode. The event count mode is used to count external events, which means that the clock source comes from an external (TMR) pin. The A/D clock mode is used to count external A/D clock, the RC oscillation mode is decided by ADCR register. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on the instruction clock. In the event count, A/D clock or internal timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter (TMRAH and TMRAL) to FFFFH. Once overflow occurs, the counter is reloaded from the timer/event counter preload register (TMRBH and TMRBL) and generates the corresponding interrupt request flag (TF; bit 4 of INTC1) at the same time. In the pulse width measurement mode with the TON and TE bits are equal to 1, once the TMR has received a transient from low to high (or high to low if the TE bit is 0) it will start counting until the TMR returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that in this operation mode, the timer/event counter starts counting not according to the logic level but according to the transient
D a ta B u s O v e r flo w T R Q P.D
TN TN TN TO N
1 0
2
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
R e lo a d P A 3 D a ta C T R L
Timer/event counter
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HT47C20
Label (TMRC) Bits 3/4 TE TON 0~2 3 4 Unused bit, read as 0 Defines the TMR active edge of timer/event counter (0=active on low to high; 1=active on high to low) Enable/disable timer counting (0=disabled; 1=enabled) Defines the operating mode (TN2, TN1, TN0) 000= Timer mode (system clock) 001= Timer mode (system clock/4) 010= Timer mode (RTC output) 011= A/D clock mode (RC oscillation decided by ADCR register) 100= Event counter mode (external clock) 101= Pulse width measurement mode (system clock/4) 110= Unused 111= Unused TMRC register edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues interrupt request just like the other three modes. To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON will be automatically cleared after the measurement cycle is completed. But in the other three modes, the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider) output at PA3 by mask option. No matter what the operation mode is, writing a 0 to ETI can disable the corresponding interrupt service. When the PFD function is selected, executing CLR PA.3 instruction to enable PFD output and executing SET PA.3 instruction to disable PFD output and PA.3 output low level. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter turns on, data written to the timer/event counter preload register is kept only in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs. When the timer/event counter (reading TMRAH) is read, the clock will be blocked to avoid errors. As this may results in a counting error, this must be taken into consideration by the programmer. It is strongly recommended to load first the desired value for TMRBL, TMRBH, TMRAL, and TMRAH registers, before turning on the related timer/event counter for proper operation. Because the initial value of TMRBL, TMRBH, TMRAL and TMRAH are unknown. If the timer/event counter is on, the TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written to. Only when the timer/event counter is off and when the instruction MOV is used could those four registers be read or written to. Function
TN0 TN1 TN2
5 6 7
Example for Timer/event counter mode (disable interrupt): clr tmrc clr adcr.1 clr intc1.4 mov a, low (65536-1000) mov tmrbl, a mov a, high (65536-1000) mov tmrbh, a mov a, 00110000b mov tmrc, a ; timer clock source=T1 and timer on ; set timer mode ; clear timer/event counter interrupt request flag ; give timer initial value ; count 1000 time and then overflow
p10: clr wdt
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HT47C20
snz intcl.4 jmp p10 ; polling timer/event counter interrupt request flag
clr intcl.4
; clear timer/event counter interrupt request flag ; program continue
A/D converter Two channels of RC type A/D converter are implemented in the HT47C20. The A/D converter contains two 16-bit programmable count-up counter and the Timer A clock source may come from the system clock, instruction clock or RTC output. The timer B clock source may come from the external RC oscillator. The TMRAL, TMRAH, TMRBL, TMRBH is composed of the A/D converter when ADC/TM bit (bit 1 of ADRC register) is 1. The A/D converter timer B clock source may come from channel 0 (IN0 external clock input mode, RS0~CS0 oscillation, RT0~CS0 oscillation, CRT0~CS0 oscillation (CRT0 is a resistor), or RS0~CRT0 oscillation (CRT0 is a capacitor) or channel 1 (RS1~CS1 oscillation, RT1~CS1 oscillation or IN1 external clock input). The timer A clock source is from the system clock, instruction clock or RTC prescaler clock output decided by TMRC register. There are six registers related to the A/D converter, i.e., TMRAH, TMRAL, TMRC, TMRBH, TMRBL and ADCR. The internal timer clock is input to TMRAH and TMRAL, the A/D clock is input to TMRBH and TMRBL. The OVB/OVA bit (bit 0 of ADCR register) decides whether timer A overflows or timer B overflows, then the TF bit is set and timer interrupt occurs. When the A/D converter mode timer A or timer B overflows, the TON bit is reset and stop counting. Writing TMRAH/TMRBH makes the starting value be placed in the timer A/timer B and reading TMRAH/TMRBH gets the contents of the timer A/timer B. Writing TMRAL/TMRBL only writes the data into a low byte buffer, and writing TMRAH/TMRBH will write the data and the contents of the low byte buffer into the timer A/timer B (16-bit) simultaneously. The timer A/timer B is changed by writing TMRAH/TMRBH operations and writing TMRAL/TMRBL will keep timer A/timer B unchanged.
R e a d i n g T M R A H / T M R B H w i l l a l so l a t ch t h e TMRAL/TMRBL into the low byte buffer to avoid the false timing problem. Reading TMRAL/TMRBL returns the contents of the low byte buffer. In other word, the low byte of timer A/timer B can not be read directly. It must read the TMRAH/TMRBH first to make the low byte contents of timer A/timer B be latched into the buffer. If the A/D converter timer A and timer B are counting, the TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written to. To avoid conflicting between timer A and timer B, the TMRAH, TMRAL, TMRBH and TMRBL registers should be accessed with MOV instruction under timer A and timer B off condition. The bit4~bit7 of ADCR decides which resistor and capacitor compose an oscillation circuit and input to TMRBH and TMRBL. The TN0, TN1 and TN2 bits of TMRC define the clock source of timer A. It is recommended that the clock source of timer A use the system clock, instruction clock or RTC prescaler clock. The TON bit (bit 4 of TMRC) is set 1 the timer A and timer B will start counting until timer A or timer B overflows, the timer/event counter generates the interrupt request flag (TF; bit 4 of INTC1) and the timer A and timer B stop counting and reset the TON bit to 0 at the same time. If the TON bit is 1, the TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written to. Only when the timer/event counter is off and when the instruction MOV is used could those four registers be read or written to.
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HT47C20
Label (ADCR) Bits Function In the RC type A/D converter mode, this bit is used to define the timer/event counter interrupt which comes from timer A overflow or timer B overflow. (0= timer A overflow; 1= timer B overflow) In the timer/event counter mode, this bit is void. Defines 16 timer/event counters or RC type A/D converter is enabled. (0= timer/event counter enable; 1= A/D converter is enabled) Unused bit, read as 0. Defines the A/D converter operating mode (M3, M2, M1, M0) 0000= IN0 external clock input mode 0001= RS0~CS0 oscillation (reference resistor and reference capacitor) 0010= RT0~CS0 oscillation (resistor sensor and reference capacitor) 0011= CRT0~CS0 oscillation (resistor sensor and reference capacitor) 0100= RS0~CRT0 oscillation (reference resistor and sensor capacitor) 0101= RS1~CS1 oscillation (reference resistor and reference capacitor) 0110= RT1~CS1 oscillation (resistor sensor and reference capacitor) 0111= IN1 external clock input mode 1XXX= Undefined mode ADCR register
S1 S y s te m S y s te m RTC C lo c k S2 C lo c k /4 S3 O u tp u t TON O V B /O V A = 1 T im e r B R esetTO N T im e r A O V B /O V A = 0 In te rru p t
OVB/OVA
0
ADC/TM 3/4
1 2~3
M0 M1 M2 M3
4 5 6 7
S12 S13
S4 IN 0 CS0
S5
S6 CRT0
S7 RS0
S8 RT0 IN 1 S9 CS1 S10 RS1 S11 RT1
TN2 0 0 0 O th e r
TN1 0 0
TN0 0 1
S1 1 0
S2 0 1
S3 0 0
M3 0 0
M2 0 0
M1 0 0
M0 0 1
S4 0 1
S5 0 0
S6 0 0
S7 0 1
S8 0 0
S9 0 0
S10 0 0
S11 0 0
S12 1 1
S13 0 0
1
0 0
0 0
0 0
1 0 0 0 0 0 1
0 0 1 1 1 1
0 1 0 0 1 1
1 1 0 1 0 1
0 1 0 0 0 0 0
1 0 1 0 0 0 0
0 1 0 0 0 0 0
0 0 1 0 0 0 0
0 0 0 0 0 0 0
1 0 0 1 1 0 0
0 0 0 1 0 0 0
0 0 0 0 1 0 0
0 1 1 0 0 0 0
1 0 0 1 1 1 0
0
N o te : 0 = o ff, 1 = o n
N o te : 0 = o ff, 1 = o n
RC type A/D converter
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HT47C20
Example for RC type AD converter mode (Timer A overflow): clr tmrc clr adcr.1 clr intc1.4 mov a, low (65536-1000) mov tmrbl, a mov a, high (65536-1000) mov tmrbh, a mov a, 00010010b mov adcr,a mov a, 00h mov tmrbl, a mov a, 00h mov tmrbh, a ; give timer B initial value ; RS0~CS0; set RC type ADC mode; set Timer A overflow ; set timer mode ; clear timer/event counter interrupt request flag ; give timer A initial value ; count 1000 time and then overflow
mov a, 00110000b mov tmrc, a p10: clr wdt snz intcl.4 jmp p10 clr intcl.4
; timer A clock source=T1 and timer on
; polling timer/event counter interrupt request flag
; clear timer/event counter interrupt request flag ; program continue
Example for RC type AD converter mode (Timer B overflow): clr tmrc clr adcr.1 clr intc1.4 mov a, 00h mov tmrbl, a mov a, 00h mov tmrbh, a ; set timer mode ; clear timer/event counter interrupt request flag ; give timer A initial value
mov a, 00010011b mov adcr,a
; RS0~CS0; set RC type ADC mode; set Timer B overflow
mov a, low (65536-1000) mov tmrbl, a mov a, high (65536-1000) mov tmrbh, a
; give timer B initial value ; count 1000 time and then overflow
mov a, 00110000b mov tmrc, a
; timer A clock source=T1 and timer on
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HT47C20
p10: clr wdt snz intcl.4 jmp p10 ; polling timer/event counter interrupt request flag
clr intcl.4
; clear timer/event counter interrupt request flag ; program continue
Input/output ports There are 8-bit bidirectional input/output port and 4-bit input port in the HT47C20, labeled PA and PB which are mapped to the data memory of [12H] and [14H] respectively. The high nibble of the PA is NMOS output and input with pull-high resisters. The low nibble of the PA can be used for input/output or output operation by selecting NMOS or CMOS output by mask option. Each bit on the PA can be configured as a wake-up input, and the low nibble of the PA with or without pull-high resistor by mask option. PB can only be used for input operation, and each bit on the port is with pull high resistor. Both are for the input operation, these ports are non-latched, that is, the inputs should be ready at the T2 rising edge of the instruction MOV A, [m] (m=12H or 14H). For PA output operation, all data are latched and remain unchanged until the output latch is rewritten. When the structures of PA are open drain NMOS type, it
should be noted that, before reading data from the pads, a 1 should be written to the related bits to disable the NMOS device. That is done first before executing the instruction MOV A, 0FFH and MOV [12H], A to disable related NMOS device, and then MOV A, [12H] to get stable data. After chip reset, these input lines remain at a high level or are left floating (by mask option). Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. Each bit of the PA output latches can not use these instruction, which may change the input lines to output lines (when input line is at low level).
V
DD
V
DD
V
DD
V
DD
W EAK P u ll- u p D a ta B u s WR C h ip R e s e t D CK S Q M U X Q B Z O p tio n M ask O p tio n D a ta B u s P A 0 /B Z WR D CK S Q M U X Q B Z O p tio n M ask O p tio n
W EAK P u ll- u p
P A 1 /B Z
C h ip R e s e t
B Z S ig n a l M R e a d P a th X S y s te m M a s k O p tio n W a k e -u p M a s k O p tio n U M U X
R e a d P a th
S y s te m
W a k e -u p
PA0/BZ, PA1/BZ input/output port
Rev. 1.60
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HT47C20
IR DATA BUS WR C h ip R e s e t X P.D S ig n a l D CK S Q M U Q O p tio n V V
DD DD
W EAK P u ll- u p M a s k O p tio n P A 3 /P . D
M ask O p tio n
M R e a d P a th X U
S y s te m
W a k e -u p M a s k O p tio n
PA2/IR, PA3/PFD input/output port
V
DD
W EAK P u ll- u p
V
DD
D a ta B u s W r ite C h ip R e s e t R e a d I/O S y s te m W a k e -u p
D CK S Q
Q
PA4~PA7
W EAK P u ll- u p
R e a d D a ta D a ta B u s
M a s k O p tio n
PB0~PB3
PA4~PA7 input/output ports LCD display memory The HT47C20 provides an area of embedded data memory for LCD display. The LCD display memory is designed into 204 bits. If the LCD selected 194 segments output, the 53H of the LCD display memory can not be accessed. This area is located from 40H to 53H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the data memory) is the switch between the general data memory and the LCD display memory. When the BP is set 1 any data written into 40H~53H will effect the LCD display (indirect addressing mode using MP1).
COM 0 1 2 3 40H 41H 42H 43H
PB input lines When the BP is cleared 0, any data written into 40H~53H means to access the general purpose data memory. The LCD display memory can be read and written only by indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the HT47C20.
51H 52H 53H 0 1 2 3 B it
SEGMENT
0
1
2
3
17
18
19
Display memory (bank 1)
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HT47C20
LCD driver output The output number of the HT47C20 LCD driver can be 203 or 194 by mask option (i.e., 1/3 duty or 1/4 duty). The bias type of the LCD driver is C type. A capacitor mounted between C1 and C2 pins is needed. The bias voltage of the LCD driver can be 1/2 bias or 1/3 bias by mask option. If 1/2 bias is selected, a capacitor mounted between V3 pin and the ground is required. If 1/3 bias is selected, two capacitors are needed for V1 and V3 pins. Refer to the application diagram.
1 /3 b ia s C1 C2 V1 1 /2 b ia s C1 C2 V1 V V2 V3 V
V2 V3
DD
DD
V1, V2, V3 application diagram
D u r in g a R e s e t P u ls e : C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts
VD 1 /2 VS VD 1 /2 VS S S VD 1 /2 VS VD 1 /2 VS VD 1 /2 VS VD 1 /2 VS VD 1 /2 VS VD 1 /2 VS VD 1 /2 VS VD 1 /2 VS VD 1 /2 VS VD 1 /2 VS VD 1 /2 VS S VD 1 /2 VS VD 1 /2 VS S
D D D S D S D D D D D D S D D D S S S S S S S
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
N o r m a l O p e r a tio n M o d e : COM0 COM1 COM2 L C D s e g m e n ts o n C O M 0 ,1 ,2 s id e s b e in g u n lit O n ly L C D s e g m e n ts o n C O M 0 s id e b e in g lit O n ly L C D s e g m e n ts o n C O M 1 s id e b e in g lit O n ly L C D s e g m e n ts o n C O M 2 s id e b e in g lit L C D s e g m e n ts o n C O M 0 ,1 s id e s b e in g lit L C D s e g m e n ts o n C O M 0 ,2 s id e s b e in g lit L C D s e g m e n ts o n C O M 1 ,2 s id e s b e in g lit L C D s e g m e n ts o n C O M 0 ,1 ,2 s id e s b e in g lit H a lt M o d e : C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts
D S D
VDD VDD
LCD driver output (1/3 duty, 1/2bias)
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HT47C20
3 /2 V D D VDD 1 /2 V D D COM0 VSS 3 /2 V D D VDD 1 /2 V D D COM1 VSS 3 /2 V D D VDD 1 /2 V D D COM2 VSS 3 /2 V D D VDD COM3 1 /2 V D D VSS 3 /2 V D D VDD L C D s e g m e n ts O N C O M 2 s id e lig h te d 1 /2 V D D VSS
LCD driver output (1/4 duty, 1/3 bias)
Rev. 1.60
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HT47C20
Buzzer HT47C20 provides a pair of buzzer output BZ and BZ, which share pins with PA0 and PA1 respectively, as determined by mask option. Its output frequency can also be selected by mask option. When the buzzer function is selected, setting PA.0 and PA.1 0 simultaneously will enable the buzzer output and setting PA.0 1 will disable the buzzer output and setting PA.0 0 and PA.1 1 will only enable the BZ output and disable the BZ output. PA1 0 (CLR PA.1) 1 (SET PA.1) X PA0 0 (CLR PA.0) 0 (CLR PA.0) 1 (SET PA.0) Buzzer enable IR carrier HT47C20 provides carrier driving capability that allows for easy interfacing to an infrared diode, which share pin with PA2, as determined by mask option. Function PA0=BZ, PA1=BZ PA0=BZ, PA1=0 PA0=0, PA1=0 Programmable frequency divider 3/4 PFD The PFD output shares pin with PA3, as determined by mask option. When the PFD option is selected, setting PA3 0 (CLR PA.3) will enable the PFD output and setting PA3 1 (SET PA.3) will disable the PFD output and PA3 output at low level. PFD output frequency = 1 1 2 timer overflow period PA3 0 (CLR PA.3) 1 (SET PA.3) Function PA3= PFD output PA3= 0 When the carrier option is selected, setting PA2 0 (CLR PA.2) will enable the carrier output and setting PA2 1 (SET PA.2) will disable the carrier output and the PA2 output is at low level. The IR carrier frequency is system clock divided by 12 and it is 1/4 duty. PA2 0 (CLR PA.2) 1 (SET PA.2) Function PA2=IR carrier output PA2=0
Register
Bit No. 0 1 2 3
Label RT0 RT1 RT2 3/4
Read/Write R/W 3/4
Reset 1 1 1 3/4
Function 8 to 1 multiplexer control inputs to select the real time clock prescaler output Unused bit, this bit must clear to 0 Control the RTC OSC to oscillate quickly. 0 enable 1 disable After power on, set this bit to 1 to reduce power consumption Unused bit, this bit is unknot for reading Unused bit, read as 0
RTCC (09H)
4
SAVE
R/W
0
5 6, 7
3/4 3/4
3/4 3/4
3/4 3/4
RTCC Register
Rev. 1.60
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HT47C20
Mask option The following shows many kinds of mask options in the HT47C20. All these options should be defined in order to ensure proper system functioning. No. 1 2 3 4 Mask Option OSC type selection. This option is to decide if an RC or a crystal oscillator is chosen as system clock. Clock source selection of WDT, RTC and Time Base. There are three types of selection: system clock/4 or RTC OSC or WDT OSC. WDT enable or disable selection. WDT can be enabled or disabled by mask option. CLR WDT times selection. This option defines how to clear the WDT by instruction. One time means that the CLR WDT can clear the WDT. Two times means that only if both of the CLR WDT1 and CLR WDT2 have been executed, then WDT can be cleared. Time Base time-out period selection. The Time Base time-out period ranges from fS/212 to fS/215. fS means the clock source selected by mask option. Buzzer output frequency selection. There are eight types frequency signals for buzzer output: fS/22~fS/29. fS means the clock source selected by mask option. Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT mode by a following edge. Pull high selection. This option is to decide whether the pull high resistance is viable or not on the low nibble of the PA. PA CMOS or NMOS selection. The structure of the low nibble of the PA can be selected to be CMOS or NMOS. When the CMOS is selected, the related pins only can be used for output operations. When the NMOS is selected, the related pins can be used for input or output operations. I/O pins share with other function selection. PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs. PA2/IR: PA2 can be set as I/O pins or IR carrier output. PA3/PFD: PA3 can be set as I/O pins or PFD output. LCD common selection. There are two types of selection: 3 commons (1/3 duty, 1/2 bias) or 4 commons (1/4 duty, 1/3 bias). If the 4 commons is selected, the segment output pin SEG19/COM3 will be set as a common output COM3. LCD driver clock selection. There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. fS means the clock source selection by mask option. LCD on or LCD off at the HALT mode selection. The LCD can be enable or disable at the HALT mode by mask option.
5 6 7 8
9
10
11
12 13
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HT47C20
Application Circuits
R C o s c illa to r a p p lic a tio n (1 /3 b ia s )
OSC1 51kW ~1M W OSC2 V 100kW
RES
DD
C r y s ta l o s c illa to r a p p lic a tio n (1 /3 b ia s )
300p. OSC1 SEG 0~18 CO M 0~3 C1 C2 V 0 .1 m . V 0 .1 m .
DD
LCD PANEL 0 .1 m . 300p.
4 5 5 k H z /4 8 0 k H z OSC2
DD
SEG 0~18 CO M 0~3 C1 C2 V1
LCD PANEL 0 .1 m .
V1
100kW
RES
0 .1 m . V 0 .1 m .
DD
V2
0 .1 m .
H T47C 20
V3
0 .1 m .
V2
H T47C 20
OSC3
V3
IN 0 OSC3 32768H z OSC4 IN T TM R CS0 CRT0 RT0 RS0 IN 1 CS1 RS1 RT1 PA0~PA7 PB0~PB3 R orC 32768H z
IN 0 CS0 CRT0 R orC
OSC4
RT0 RS0
IN T TM R
IN 1 CS1 RS1 RT1 PA0~PA7 PB0~PB3
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HT47C20
R C o s c illa to r a p p lic a tio n (1 /2 b ia s )
OSC1 51kW ~1M W OSC2 V 100kW
RES
DD
C r y s ta l o s c illa to r a p p lic a tio n (1 /2 b ia s )
300p. SEG 0~19 CO M 0~2 C1 C2 V1 V2 V 100kW
DD
LCD PANEL 0 .1 m . 300p. V
OSC1 4 5 5 k H z /4 8 0 k H z OSC2
DD
SEG 0~19 CO M 0~2 C1 C2 V1
LCD PANEL 0 .1 m .
RES
V2
V
DD
0 .1 m .
H T47C 20
V3
0 .1 m .
0 .1 m .
H T47C 20
OSC3
V3
0 .1 m .
IN 0 OSC3 32768H z OSC4 IN T TM R CS0 CRT0 RT0 RS0 IN 1 CS1 RS1 RT1 PA0~PA7 PB0~PB3 R orC 32768H z
IN 0 CS0 CRT0 R orC
OSC4
RT0 RS0
IN T TM R
IN 1 CS1 RS1 RT1 PA0~PA7 PB0~PB3
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HT47C20
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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HT47C20
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PD TO(4),PD(4) TO(4),PD(4) None None TO,PD Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared. Otherwise the TO and PD flags remain unchanged.
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HT47C20
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TC2 3/4 ADCM A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,x Description Operation Affected flag(s) TC2 3/4 ADDM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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HT47C20
AND A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,x Description Operation Affected flag(s) TC2 3/4 ANDM A,[m] Description Operation Affected flag(s) TC2 3/4 CALL addr Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr
Operation Affected flag(s)
TC2 3/4 CLR [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.60
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HT47C20
CLR [m].i Description Operation Affected flag(s) TC2 3/4 CLR WDT Description Operation Affected flag(s) TC2 3/4 CLR WDT1 Description TC1 3/4 TO 0 PD 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are cleared. WDT 00H PD and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0*
Operation Affected flag(s)
TC2 3/4 CLR WDT2 Description
TC1 3/4
TO 0*
PD 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0*
Operation Affected flag(s)
TC2 3/4 CPL [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 0*
PD 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z O
AC 3/4
C 3/4
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HT47C20
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TC2 3/4 DAA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TC2 3/4 DEC [m] Description Operation Affected flag(s) TC2 3/4 DECA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
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HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PD 1 TO 0
Operation
Affected flag(s) TC2 3/4 INC [m] Description Operation Affected flag(s) TC2 3/4 INCA [m] Description Operation Affected flag(s) TC2 3/4 JMP addr Description Operation Affected flag(s) TC2 3/4 MOV A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 0 PD 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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July 26, 2002
HT47C20
MOV A,x Description Operation Affected flag(s) TC2 3/4 MOV [m],A Description Operation Affected flag(s) TC2 3/4 NOP Description Operation Affected flag(s) TC2 3/4 OR A,[m] Description Operation Affected flag(s) TC2 3/4 OR A,x Description Operation Affected flag(s) TC2 3/4 ORM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
No operation No operation is performed. Execution continues with the next instruction. PC PC+1
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
Rev. 1.60
37
July 26, 2002
HT47C20
RET Description Operation Affected flag(s) TC2 3/4 RET A,x Description Operation Affected flag(s) TC2 3/4 RETI Description Operation Affected flag(s) TC2 3/4 RL [m] Description Operation Affected flag(s) TC2 3/4 RLA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. PC Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. PC Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
Rev. 1.60
38
July 26, 2002
HT47C20
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TC2 3/4 RLCA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TC2 3/4 RR [m] Description Operation Affected flag(s) TC2 3/4 RRA [m] Description Operation Affected flag(s) TC2 3/4 RRC [m] Description Operation TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TC2 3/4 Rev. 1.60 TC1 3/4 TO 3/4 PD 3/4 39 OV 3/4 Z 3/4 AC 3/4 C O July 26, 2002
HT47C20
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TC2 3/4 SBC A,[m] Description Operation Affected flag(s) TC2 3/4 SBCM A,[m] Description Operation Affected flag(s) TC2 3/4 SDZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TC2 3/4 SDZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.60
40
July 26, 2002
HT47C20
SET [m] Description Operation Affected flag(s) TC2 3/4 SET [m]. i Description Operation Affected flag(s) TC2 3/4 SIZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TC2 3/4 SIZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TC2 3/4 SNZ [m].i Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.60
41
July 26, 2002
HT47C20
SUB A,[m] Description Operation Affected flag(s) TC2 3/4 SUBM A,[m] Description Operation Affected flag(s) TC2 3/4 SUB A,x Description Operation Affected flag(s) TC2 3/4 SWAP [m] Description Operation Affected flag(s) TC2 3/4 SWAPA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
Rev. 1.60
42
July 26, 2002
HT47C20
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TC2 3/4 SZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TC2 3/4 SZ [m].i Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TC2 3/4 TABRDC [m] Description Operation Affected flag(s) TC2 3/4 TABRDL [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.60
43
July 26, 2002
HT47C20
XOR A,[m] Description Operation Affected flag(s) TC2 3/4 XORM A,[m] Description Operation Affected flag(s) TC2 3/4 XOR A,x Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.60
44
July 26, 2002
HT47C20
Package Information
64-pin QFP (1420) outline dimensions
C D 51 33 G H
I 52 32 . A B E
64
20 K = J 1 19
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.80 13.90 24.80 19.90 3/4 3/4 2.50 3/4 3/4 1.15 0.10 0 Nom. 3/4 3/4 3/4 3/4 1 0.40 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.45 0.20 7
Rev. 1.60
45
July 26, 2002
HT47C20
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.60
46
July 26, 2002

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